1. Field of the Invention
This invention relates generally to semiconductor processing, and, more particularly, to forming a hetero-structured, inverted-T field effect transistor.
2. Description of the Related Art
The constant drive to increase the density of semiconductor devices that can be formed on a wafer and the speed at which these devices operate has led to many modifications in the structure of conventional semiconductor devices. For example, as development goals have approached the 22 nm node, attempts to maintain a conventional planar device scaling have encountered roadblocks including inadequate control of the channel region by the gate electrode, which may lead to short channel effects. Multi-directional control of the channel may allow increased immunity to short channel effects such as sub threshold slopes, drain induced barrier leakage, and the like. Many semiconductor devices may therefore be formed using multigate field effect transistors (FETs). One example of a multi-gate FET incorporates a gate structure formed from an ultrathin body (UTB) that is turned on end relative to conventional planar gate structures (i.e., the UTB gate structure is perpendicular to the substrate). These devices are conventionally referred to as Fin-FETs because of the fin-like shape of the structures that connect the source and drain regions of the Fin-FETs to the gate structure. The Fin-FET devices may offer a means of packing more current (and consequently more speed) into each unit area of a chip while keeping the processing, materials, and circuit design factors relatively consistent with previous technology nodes.
FIGS. 1A, 1B, and 1C conceptually illustrate a conventional method of forming fin structures in a Fin-FET. These figures depict a cross-sectional view 100 of the material layers used to form the fin structures. In the embodiment shown in FIG. 1A, a layer 105 of semiconductor material (e.g., monocrystalline silicon, silicon germanium, or germanium) is formed over a dielectric layer 110 (e.g., silicon dioxide). An oxide layer 115 is then formed over the layer of semiconductor material 105. The oxide layer 115 may serve as a protective layer for the layer 105 for subsequent forming and/or etching of other structures. The oxide layer 115 may also serve as a stress reduction layer for subsequently deposited layers, such as nitride layers. In some embodiments, another nitride layer 120 is deposited. A photoresist layer, which is patterned, using e.g. a mask, is then formed over the nitride layer and is used to transfer the pattern to the nitride layer. The patterned nitride layer 120 is used as a mask to etch the oxide layer 115 and the layer 105 to form the fin structures 125 shown in FIG. 1B. In one embodiment, the patterned nitride layer 120 and the oxide layer 115 may be removed to leave behind the fin structures 125 shown in FIG. 1C.
FIG. 2 conceptually illustrates a top-down view of a conventional transistor 200 formed using Fin-FET techniques. The transistor 200 includes a gate electrode 205 that is positioned between a source 210 and a drain 215. The fin structures 220, such as the thin structures 125 shown in FIGS. 1A-C, have been formed between the source 210 and the drain 215, and these structures extend underneath the gate electrode 205. Examples of Fin-FETs and the techniques that may be used to form Fin-FETs are found in Rao and Mathew (U.S. Pat. No. 7,265,059), Burnett, et al. (U.S. Patent Application Publication No. 2007/0161171), and Harris, et al. (“Fin-FETs: Challenges in Material and Processing for a New 3-D Device Paradigm,” FUTURE FAB International, Issue 23).
The fin structures in conventional Fin-FETs may be configured to provide relatively high drive currents for the CMOS devices that incorporate the Fin-FETs. However, the conventional fin structures have a single orientation and are formed of a single material. Consequently, conventional fin structures can only be optimized to provide high drive currents for a single type of CMOS device, i.e. the fin structures can be optimized for either a PMOS device where high hole mobility is desired or an NMOS device where high electron mobility is desired. Most circuit designs include large numbers of both PMOS and NMOS devices. The process flows used to form the circuit may be optimized for one type of device, but this may also result in a less than optimal process flow for the other type of device.
The subject matter described herein is directed to addressing the effects of one or more of the problems set forth above.